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Example-b8-3
- 学习使用DO文件进行仿真的基本方法,根据ModelSim提供的命令或者Tcl/Tk语言的语法，将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中，然后直接执行这个DO文件，就可以完成整个仿真流程-DO learn how to use basic file simulation method, according to the syntax of the command or ModelSim provides Tcl/Tk language will flow simulation
fifo2
- 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
MSK
- FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页-MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation blo
DSB
- FPGA中实现的DSB的AM调制，带Modelsim仿真，实际测试通过：载波频率，信号频率以及调制度可调。-The FPGA implemented in the DSB AM modulation with Modelsim simulation, the actual test: the carrier frequency, and modulation signal frequency is adjustable.
FSK
- FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。-FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.
BPSK
- FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调-FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable
force
- modelsim force 命令例子-modelsim force
fft_8
- 基二8点fftverilog实现。经过modelsim仿真通过-Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation
ChengFaQi_mux16
- 实现16位乘法器 并有modelsim仿真文件-The realization of the 16 bit multiplier and Modelsim simulation file!!!!!!!!!!!!!!!!!!!!!!!!
lab1
- 初步掌握ModelSim的使用方法,了解TestBench的编写,Verilog HDL的层次设计方法/参数设置、参数传递方法.-Preliminary master the use of ModelSim understand TestBench preparation, Verilog HDL level design methods/parameters, parameter passing methods.
FSM
- 用verilog语言编写的状态机，包括状态机的各种标准写法，包括了modelsim的整个工程。-This code is used to describe the FSM. And it includes all modes of it.
code
- c++语言转verilog语言，程序员不需要学习verilog即可对fpga原型进行快速仿真，本例为catapult c语言的fft程序，可以利用catapult转换工具转成verilog语言， 用modelsim进行仿真，并且可以加各种约束。-c++ program translate verilog program。
testcordic
- catapult c cordic程序，可以转换成verilog语言，完成用modelsim进行仿真，结果可以与matlab进行比较。-catapult c cordic program
cbf
- catapult c 常规波束形成程序，已转化为verilog语言，并且完成modelsim验证-catapult c beamforming program
comp
- 四位比较器，用verilog语言编写，在modelsim软件中编译仿真成功，可以下载-Four comparators, using verilog language, compiled simulation in modelsim software successfully, you can download to see
MIPSCPU
- 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
tlv2553 verilog
- tlv2553 verilog TI 的ad转换芯片 在modelsim 上进行波形仿真
tlv2553
- verilog tlv2553 TI公司的ad芯片 在modelsim上进行波形仿真-verilog tlv2553
ii2c
- IIC数据总线的verilog代码，已用modelsim测试通过。-IIC data bus verilog code, has passed the test with modelsim.
cic_cz
- 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co