搜索资源列表
REALTEK WIFI DRIVER
- REALTEK WIFI DRIVER chipset RTL8188EUS,RTL8189ES
ambartl
- amba总线的rtl代码，仿真用，不可综合。(AMBA bus RTL code, simulation, can not be integrated.)
RTL8812AU_linux_v4.3.20_16317_20160108
- RTL88x2 wifi无线网卡驱动，适用于linux2.6.x 3.x平台，使用平台指定交叉编译工具编译即开使用，编译为ko文件(The RTL88x2 wifi wireless card driver is applicable to the linux2.6. X 3. X platform, which USES the platform to specify the cross-compilation tool to compile and use, and compiles the
8051
- The resource code of The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system
si四位加法器
- 内含三个普通的四位加法器，adder，adder4-2，adder4-3(library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity full_adder is port( a,b,ci :in std_logic; s,co :out std_logic); end entity; architecture rtl of full_adder is begin s&
modol
- 蓝牙的一个ip RTL 核,不知道对大家有没有用？谢谢,()
8051Core
- 8051 Core Verilog RTL IP Code
rtl
- 实现AD7606数据采集，基于xilinx的6系列(Realization of AD7606 data acquisition)
rtl
- Learn the code freely to provide everyone with learning and hope to help everyone. Thank you
NIOS设计从入门到精通
- nios大神进阶，一本非常好的FPGA书籍，从RTL到eclips(nios tech.a very good book learning FPGA tech.)
8051 Verilog Code
- 8051 Core Verilog RTL code
AES128 Verilog Code
- AES128 Encryption/Decryption Verilog RTL Code
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving prop
apb_timer.tar
- 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr
RISC
- URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)
dpd_v6_0_example_design
- rtl代码级的dpd 参考代码 包含六个文件夹分别为： 1.clk_gen 2.device,器件信息 3.dpd v6.0,rtl代码. 4.package 5.platform 6.rf_board
formal_verification
- 现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
ppm编解码器
- 进行ppm编解码的verilog代码，RTL描述(Verilog code for ppm encoding and decoding, RTL descr iption)