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DECOORG
- vhdl codings of decoder. data flow modelling, structural and behavioral modelling codes with their output waveform and rtl schematic.
pci_32tlite_oc
- 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
IU3
- sun公司的sparc结构之整数处理器vhdl源码-The file is the RTL of the Sparc s integer unit.
rtl
- this the generation of 48 pulses implementation in hdl language-this is the generation of 48 pulses implementation in hdl language
IIR
- 实验说明： 本次实验实现一个IIR滤波器，并在ISE里面仿真。 project目录里面是工程-Experiment descr iption: this experiment to achieve an IIR filter, and the ISE inside the simulation. \ rtl directory which is the source file \ project directory which is the project
seg
- 程序说明: 本次实验控制开发板上面的数码管。 \1-f文件夹里面的程序控制数码管从1开始显示，逐渐加1，一直到f。 \1234文件夹里面的程序控制数码管显示1234。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Descr iption: This development board above th
uart
- 程序说明: 本次实验控制开发板上面的串口，与PC机进行通信，并在串口精灵里面显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: The experimental control development board above the serial port to communicate wit
usb
- 程序说明: 本次实验控制开发板USB，与PC机进行通信，并在显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display char
rtl
- 基于脉动结构的有限域乘法器，verilog代码-Based on the pulse of the structure of finite field multipliers, verilog code
GenDEC.RTL
- Tristate Bus -Tristate Bus Tristate Bus
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
LIP6492CORE_zigzag
- Compression ZingZang RTL Verilog source code
mem-ctrl-rtl
- 实现对ddr的控制，可以在fpga的仿真环境下跑程序，并有testbench可以参考-implement ddr control
mem-if-rtl
- 实现memory的interface，就是memory的接口实现，可以在fpga上进行综合仿真-Achieve the memory of the interface, is the memory of the interface, you can fpga on the integrated simulation
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.
mc8051_top
- 利用synplify8.1综合的8051IPcore电路图，可用synplify打开查看电路-8051 RTL Schematic
cwdl374s
- cc386编译器源代码的最新版本，其他参照其英文说明-This package is the sources for my DOS C compiler and related tools. See license.txt and copying for licensing information See relnotes.doc for release notes use pkunzip-d to install these files These co
CoreCORDIC_DS
- cordic rtl generator for generating different cordic arithmetic