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sl.v
- 路灯控制器 采用了状态机的概念编程，其中采用了信号检测进程防止干扰信号驱动芯片工作-lights controller state machine used the concept of programming, where the signal detection processes to prevent signal interference driver chips work
lf_decode
- 检测BT.656视频格式中内含的同步信号，可分离出行场同步信号。-detection R BT.656 video format containing the synchronization signal separable travel market synchronous signal.
mnxhjc
- 本实验用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能。-this experiment + DA conversion method of comparison to the outside world analog signal detection, while such joint CPLD devices can be replaced with low-frequency AD converter functions.
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
VHDL2
- 序列信号发生器： 在系统时钟的作用下能够循环产生一组或多组序列信号的时序电路，（循环产生一组序列信号0111010011011010） 序列检测器： 检测一组或多组又二进制码组成的脉冲序列信号，当序列检测器连续收到一组或多组序列信号，如果与预先设置的码11010相同的时候，输出1，否则输出0. -Sequence of signal generator: the role of the system clock cycle to generate one or more si
miller
- 整个系统分为两个模块：检测模块和解码模块。检测模块主要完成从输入串行序列判断出A，B或C信号，并分别输出脉冲标志脉冲串Signal_A，Signal_B和Signal_C；同时，当检测到任一信号时，BIT_EN_temp输出一个高脉冲。解码模块根据检测模块输出的三个标志脉冲进行0/1解码，输出最终的密勒解码数据DOUT；同时，输出DATA_EN和BIT_EN两个标志信号。-The whole system is divided into two modules: detection module
sequence_inspector
- 序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号，这在数字通信领域中有广泛的应用。当序列检测器连续收到一组二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到连续的检测中收到每一位都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。并附有测试程序-Sequence detector can be used to detect one or
FPGA
- 将立体杂波图应用于气象杂波的CFAR处理，根据当前杂波环境的变化实时地产生杂内杂外标志，从而选择不同的信号处理支路处理当前气象杂波，提高了雷达的检测性能，降低了虚警概率。-Will be applied to three-dimensional meteorological clutter Clutter Map CFAR of treatment, according to the current clutter environment generated in real time with
VHDL
- DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage si
miller
- 用ISE编写的VERILOG语言的米勒解码器的检测部分，检测四种解码信号。程序通过综合，但是仿真结果有点偏差，欢迎高手指点。-ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice
jcq
- vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
DDS
- 这是一个任意频率的正弦信号发生器，具有可改变输出信号频率，输出信号相位，任意转换输出信号类型（正弦、余弦、锯齿波、方波），屏幕可分别显示用户设定的信号频率与输出信号检测频率。-This is an arbitrary frequency sinusoidal signal generator, with can change the output signal frequency, the output signal phase, arbitrary conversion output sign
detect_signal
- 此程序完成一个序列检测的功能，检测10010序列，适当改进，可以用于FPGA中信号检测-This process is complete a sequence of test functions, test 10010 sequence, appropriate improvements can be used for FPGA in the signal detection
uart
- vhdl编写，完成了uart的接口设计，包括信号检测，判决等-vhdl prepared to complete the uart interface design, including signal detection, decision, etc.
cpld
- CPLD 语言VHDL，实现对电机位置信号检测和输出驱动-CPLD language VHDL, to realize the motor position signal detection and output drive
EDA3
- 实验目的 1．学习一般有限状态机的设计； 2．实现串行序列的设计。 二、设计要求 1． 先设计0111010011011010序列信号发生器； 2． 再设计一个序列信号检测器，若系统检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。 -Purpose of the experiment 1. Learning the general design of finite state machine 2. Serial sequence de
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
signaltext
- 信号检测，有模数转换芯片驱动，32点周期积分，判决门限2048-Signal detection, analog-to-digital conversion chip driver, 32-point cycle integral, decision threshold 2048
signal-energy-time--test
- 信号到达时间、脉宽检测，能量检测代码，包含tesebench测试文件-The signal arrival time, pulse width detection, energy detection code, including the tesebench test file