搜索资源列表
sdram_controller_latest.tar
- This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
dac5628
- DAC5628的VHDL编码及应用的verilog代码。-DAC5628 VHDL coding and applications verilog code.
verilog
- 用verilog设计的存储器，可以读入数据，读出数据，是集成电路重要运用单元-Design with verilog memory that can be read into the data, read data is important IC with Cell
verilog2
- 内含verilog常用基础部件，可以让新手得心应手，跟快体会verilog,积极思考。-Containing the Verilog common basic components, allows novice handy with fast appreciate Verilog, positive thinking.
twoBitAdder
- N-bit adder implemented in verilog
demo_axi3_memory
- axi, ahp, app, verilog, integarader
miaobiao
- 用verilog语言在FPGA上实现秒表数码管显示-Implemented on FPGA using Verilog language stopwatch digital display
wishbone-slave-and-master-to-avalon-bus
- wishbone slave and master to avalon bus verilog
PID2
- PID控制器，可以应用在数字控制的BUCK型DCDC中。-PID CONTROLLER
key
- advanced encryption key
uvm_ref_flow_1.1.tar
- ovm2uvm migration, full documentation for migration process from ovm 2uvm
filter
- verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
timegenetator
- 显示控制器时序产生代码，用于产生水平与垂直方向的同步信号-the timing generator to generate the vertical and horizontical sync signal
fpga
- 投币电路设计，投入1元，0.5元不等，出票，找币-Coin circuit design, put one yuan and 0.5 yuan per ticket, looking for money
mipsfiles
- 多周期的cpu 中alu模块设计 打算打打msn代码三年大开杀戒-cpu alu
sdi_vga
- 输出VGA显示行、场、帧有效信号，VGA显示-Output VGA display line, field, frame valid signal
waveform
- 老化仪的内部代码，是的，很好，可以下载一下看看，会有用的-Aging instrument' s internal code, yes, well, you can download it and see, will be useful
STM32_FPGA(FSMC)
- STM32+ARM FMSC 学习的重要资料找了很久的哦-STM32+ARM FMSC学习的重要资料
CLOCK
- FPGA实现数字钟。大学数字电路实验用的-FPGA implementation of a digital clock. University experiment with digital circuits