资源列表
2FSK调制解调的FPGA实现（VHDL）
- 2FSK调制解调的FPGA设计，基于XINLINX的ISE平台开发，采用VHDL语言设计，有设计文档，欢迎学习借鉴(The FPGA design of 2FSK modulation and demodulation, based on the ISE platform of xinlinx, is designed with VHDL language, with design documents, welcome to learn)
S02《Artix7*秘籍》MIG_DDR内存应用
- artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)
模24计数器
- 模24计数器的Quartus II文本输入设计及其test bench(Quartus II text input design and test bench of modulo 24 counter)
单周期CPU大作业-2020
- Verilog projects cpu
分频器的modelsim仿真
- 这是分频器的modelsim仿真文件源代码，这是分频器的modelsim仿真文件源代码，这是分频器的modelsim仿真文件源代码
POC
- 实现了计算机系统中作为I/O模块的POC。(It simulates the POC module which works as an I/O module in a computer system.)
drsstc
- 实现SKP/PDM功能的drsstc工程文件(DRSSTC project file for SKP / PDM)
Verilog的150个经典设计实例
- 非常有用的verilog的150个经典编程实例(150 classic programming examples of Verilog)
DPWM
- 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
crc16
- verilog 语言下的硬件CRC校验：CRC16(CRC verification in Verilog: CRC 16)
8层电梯控制器
- 自动电梯控制器，电梯内有八个输入按钮响应用户的上下楼层请求，并有八段数码管显示电梯当前所在楼层位置(there are eight input buttons in the elevator to respond to the user's request for going up and down the floor)
基于DSP和FPGA的通用数字信号处理系统设计
- 利用DSP配合FPGA为硬件架构，以DSP为数据处理核心，通过FPGA对USB、ADC和DAC等外围设备进行控制，并可实现频谱分析、数字滤波器等数字信号处理算法。(With DSP and FPGA as the hardware architecture and DSP as the data processing core, the peripheral devices such as USB, ADC and DAC are controlled by FPGA, and the digi