资源列表
Verilog秒表设计
- 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
VB_远控源代码
- VB_远控源代码 - (VB remote control source code!)
t
- 用于NI单片机电流电压采样以及显示，其中含有部分程控电流与程控电压，可用于并联限流限压电路。(It is used for sampling and displaying the current and voltage of NI single-chip microcomputer. It contains part of program-controlled current and program-controlled voltage and can be used for parallel
pl1
- 数码管仿真实例，内含例程和波形仿真，欢迎前来学习(Example of digital tube simulation)
ADC_cha
- ADC，Analog-to-Digital Converter的缩写，指模/数转换器或者模拟/数字转换器。是指将连续变量的模拟信号转换为离散的数字信号的器件。真实世界的模拟信号，例如温度、压力、声音或者图像等，需要转换成更容易储存、处理和发射的数字形式。模/数转换器可以实现这个功能，在各种不同的产品中都可以找到它的身影。(ADC Analog-to-Digital, the abbreviation of Converter fingerprint / digital converter or
libffi-6
- regregwergerw gewrgewrgewr gergewrgewrgrew
mips-cpu-master
- MIPS Implementation in Verilog. Full source code!
minirisc-master
- Implementation of the MiniRisc CPU in Verilog!
单片机超声波测距程序
- 51单片机超声波测距程序资料,包括全部的原理图设计，实物图设计，还有完整的程序(51 singlechip ultrasonic ranging program data, including all the schematic design, physical design, and complete program.)
CNT12
- 运用VHDL语言编写的可实现12进制的计数器。(A 12 - scale counter written in VHDL.)
FPGA开发全攻略
- FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
16-Bit_RCA
- 16 bit Ripple Carry Adder using vhdl on modelsim