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  1. 程序

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  2. 基于18b20单片机测温度,温度误差不大于0.2(Measuring temperature based on 18B20 single chip, The temperature error is not more than 0.2)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:36kb
    • 提供者:爱你要
  1. gate2

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  2. 二输入门代码,作业学习,数字逻辑电路答案条件好多(the ppt for study very very good)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:432kb
    • 提供者:小庆小庆
  1. crossbar

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  2. 2 master - 2 slave communication crossbar
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:15kb
    • 提供者:taso999
  1. round_robin

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  2. Round Robin priority arbiter
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:46kb
    • 提供者:taso999
  1. IP核的生成

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  2. 讲述了FPGA中IP核的使用方法,对于初学者很有帮助。(The method of using IP core in FPGA is described.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:2.94mb
    • 提供者:jihan
  1. SPI_controller

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  2. SPI controller (fpga/verilog)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:117kb
    • 提供者:taso999
  1. 基于IP核的ISE设计流程

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  2. 讲述了在ISE中如何通过建立ip核,使用ip核可以增加程序设计的效率。(In ISE, how to use the IP core can increase the efficiency of the program design by establishing the IP core.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:2.38mb
    • 提供者:jihan
  1. spi master slave

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  2. SPI master slave (fpga/verilog)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:66kb
    • 提供者:taso999
  1. Coding Files

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  2. Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:12kb
    • 提供者:kutti
  1. Coding files

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  2. The past several years have witnessed a rapid development in the wireless network area. So far wireless networking has been focused on high speed and long range applications. Zigbee technology was developed for a Wireless Personal Area Networks WPAN
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:8kb
    • 提供者:kutti
  1. Coding Files

    0下载:
  2. We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:27kb
    • 提供者:kutti
  1. Coding Files

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  2. Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-01-08
    • 文件大小:51kb
    • 提供者:kutti
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