资源列表
IEEE Standard for Verilog 2005
- this book introduces the use of Verilog HDL.
夏宇闻数字逻辑设计
- digital logic design
VHDL语言100例详解
- VHDL language 100 examples
VHDL-和-Verilog-HDL-的区别
- The difference between VHDL and Verilog HDL.
16位超前进位加法器
- 16位超前进位加法器的报告，报告里面含有主代码测试代码仿真结果(16 bit forward adder)
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
计算器
- 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)
SHA256_SYSTEM
- 利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。 硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。(The hardware (programmable logic device FPGA) is used to implement the cryptographic algorithm SHA256, and the soft core NIOSii is em
0FGvMPLlST
- 我想要飞的更高扯你扯的蛋都疼了心都慌了但是你还是要20个字(lavifiejflsi laifjl alakdjf)
27个FPGA实例源代码
- 27个实例代码，AD ,DA,频率计程序与仿真等(27 instance code:AD DA Frequency meter program and simulation)
Desktop
- 实现了3-8译码器的组合逻辑和时序逻辑，正确性已经通过了仿真验证，代码规范(The combined logic and timing logic of the 3-8 decoders are implemented. The correctness has already passed through the simulation verification, the code specification)
project_2_10010
- 检测的序列10010的一个小程序，用vivado做的(A program for detecting sequence '10010' powered by vivado 2014.4)