资源列表
fft paper
- an innovative approach for fft implementation
adder_sub_struct
- adder sub struct by vhdl
mulitiplier
- vhdl mulitiplier by vhdl
seq
- vhdl sequential logic
lcd
- lcd controler by vhdl
counter
- counter by implementation vhdl
wb_handler-1.0.1.tar
- wishbone ctrl for fgpa - wb handler
wb_counter-1.0.1.tar
- wishbone counter for fpga
vhdlspp-2.0.1.tar
- vhdl library for configuration
miniuart-1.0.0.tar
- wishbone uart controller
natebege-0.2.0.tar
- wishbone vhdl config tool
verilog
- 里面包括乘法器等多个verilog编码整理，大多数的编码应该都在内(It includes multiple Verilog coding collation, such as multiplier, and most of the codes should be included)