资源列表
帧同步
- 这是一个可以实现帧同步的编码，应用verilog编码(This is a coding that can implement frame synchronization, using Verilog coding)
ef48dc75a9a60030c622898a19b0f2d6 (1)
- 内有关于循环码的编码器的程序语言，可用quartus ii打开(There is a program language on the encoder of the loop code, which can be opened with Quartus II)
《HELLO FPGA》-项目实战篇-V1.1版
- 各种实例的FPGA实现，对学习FPGA有一定的帮助，希望大家能够采纳。(The FPGA realization of the digital clock has some help for learning FPGA, and I hope you can adopt it.)
exp1
- vhdl xinhao,..............
dds
- 基于DDS的信号源设计（包括三角波、正弦波、方波）(Design of signal source based on DDS)
VHDLwork
- 几个示例程序 用于初学者学习 比如计算器 停表之类程序(Several sample programs are used for beginners to learn)
AES 128 ECB Decryption
- Block mode related AES-EBC Encryption
AES 128 ECB Encryption
- Block mode related AES-EBC Decryption
Package for AES-128
- Block mode related AES Package
APBL
- APBL通信协议的FPGA设计，适用于高速通讯(APBL communication protocol FPGA verilog design)
uart
- FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
AHB_LITE
- AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)