资源列表
HardwareDesignAndModeling
- instruction vhdl persian
xsym
- 数码管显示,试用于初学者的源代码。希望通过(The digital tube displays the source code of the beginner. Hope to pass through)
key_led
- led verilog语言控制 使用quartus的简单实现(led ctrl it's easy)
clock
- 数字时钟，用VHDL语言设计，能调时间，整点响铃(Digital clock, designed in VHDL language, can adjust the time, the whole bell ring)
lab1
- 在vivado上测试通过的fpga流水灯(Test the passing FPGA flow lamp on vivado)
lab3
- 在vivado上测试通过的fpga分频器(FPGA frequency divider tested on vivado)
lab4
- 在vivado上测试通过的fpga滤波器(Test the FPGA filter passed on vivado)
基于STEP-FPGA板的简易数字音频播放器
- 基于FPGA的数字音频播放器，将mp3文件通过fpga并外接扬声器进行播放(FPGA based digital audio player, the MP3 file is played through the FPGA and out of the speaker.)
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
基于FPGA的嵌入式软核设计
- 基于FPGA的嵌入式软核设计，通过搭建软核实现控制(Embedded soft core design based on FPGA and control by building soft core)
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
hamming_fsk
- 基于汉明编码的fsk传输系统，含编码，调制，解调，解码等模块。(FSK transmission system based on Hamming code, including encoding, modulation, demodulation, decoding and other modules.)