资源列表
Module基础全集
- 如题，各种veirlog 基础代码大全，虽功能不及ip核，但却可以学习到很多(For example, all kinds of veirlog base code, though not as functional as IP core, can learn a lot)
example_book
- 一些简单的FPGA verilog小程序，对FPGA入门者有所帮助(Some simple FPGA Verilog small program to help beginners FPGA)
拨码开关选择
- verilog 拨码开关选择 fpga设计(verilog dfdjfjfdklf kfndsvnm)
贪吃蛇
- 都是废话电视剧方法那就回家避难硐室不烦你(dshdjsdhdhfjdskfk nbkjknl)
35_OV7725_VGA_DDR3_LX16_joint
- 多目摄像头同屏显示，实现图像分割，xilinx公司芯片，ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
Altera_lcd_color_bar_117
- altera公司飓风四代芯片，LCD屏幕彩条显示，有效实现行、场扫描。练习FPGA驱动VGA或LCD显示的入门程序(Altera hurricane four generation chip, LCD screen color display, the effective realization of line and field scanning.Practice FPGA to drive VGA or LCD display)
verilog-i2c-master
- i2cccccc masyettttttttttttt
hispi_example_design
- hispi high spededddddddddddddddd
ug901-vivado-synthesis-examples
- verilog edge detector codee, for vibado tollssssss
attachments
- fpga master fofo design continous data transmission
H_Card
- 可以用来实现生日贺卡的功能——北邮人数电实验专属代码(The function that can be used to achieve a birthday card)
4
- 设计一个轨道交通自动售票电路，只接受1，2，5元人民币，每张票价定额5元，并支持找零。要求： （1）用状态机方法设计；(Design an automatic rail transit ticketing circuit, accepting only 1, 2, 5 yuan, 5 yuan per ticket, and support change. Requirements: (1) design with state machine method;)