资源列表
wangfei
- 基于FPGA的一个LCD显示的网费计价系统设计(costing system of network)
slave_control
- VHDL实现spi，从机实现方法，实现32个bit传输，单向传输。(VHDL implementation of SPI, from the machine implementation method, the realization of 32 bit transmission, one-way transmission.)
Verilog_1Gb_DDR3_G_Die
- ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
VHDL程序
- 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)
ISCAS`89基准电路下载（包括Verilog和VHDL格式）
- SCAS `89 基准电路下载，包括Verilog和VHDL格式。verilog格式30个文件：包括S1238、S13207等;(SCAS `89 benchmark circuit downloads, including Verilog and VHDL formats. Verilog format 30 files: including S1238, S13207 and so on;)
消抖模块源代码
- 对fpga中的按键，防摔等部分进行消除抖动(To eliminate the jitter of the key in the FPGA, the fall prevention and other parts)
i2c_verilog
- i2c master controller
PHY_forPCIE
- PHY相关的用法，主要用于PCIE结构下的说明(PHY Interface for the PCI ExpressTM Architecture)
counter10
- vhdl编写的十进制计数器，名字叫count10，已配好引脚(VHDL's decimal counter, named count10, has been matched with a pin)
led
- 使用quartusII实现verilog的流水灯编程(Use quartusII to implement verilog - flow lamp programming)
ezidebug-code
- Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
FT245开发
- FT245开发 VHDL