资源列表
100-FPGA-questions-Download
- FPGA经典100问之＜下载验证16问＞。介绍了FPGA在下载验证过程中的常见问题，对FPGA常见配置电路进行了讲解。-FPGA asked the classic 100 < Download verified 16 Q> . FAQ introduced FPGA verification process the download of FPGA configuration circuit common were explained.
32mto1m
- 主要实现将32Mhz的时钟，通过一个触发信号将其分成1Mhz的互补信号，总共十个周期的，十个周期后输出为零-The main achievement of the clock 32Mhz by a trigger signal will be divided into complementary signals 1Mhz, for a total of ten cycles, after ten cycles output is zero
sport
- 基于FPGA的数字秒表，通过按键开始计时，再次按下暂停，按下复位键清零-FPGA-based digital stopwatch, through the button to start timing, press pause again, press the reset button clears
clkdiv
- 对于fpga的时钟分频，编程方法，简单易懂，赠给各位学习fpga的同志们-For fpga clock frequency division, programming method, and easy to understand, to your learning fpga comrades
uart
- UART developement in VHDL
autosell
- 自动售货机程序，以Verilog三段式描述方法描述有限状态机FSM，编译及输出正常-Vending machine program, describe the method described in Verilog three-finite state machine FSM, compile and output normal
Alarm
- The aim this project is to implement the functionality of a digital alarm clock on a FPGA. As soon as the FPGA is switched on, the clock starts. The alarm can be set using the dip-switches provided on the FPGA board. This is indicated through the LED
16-bit-crc16
- 16位并行输入输入的CRC16,已验证无错误-16-bit parallel data input crc16, algorithm logic has been verified
hello_world
- 基于nisoII软核的摇摇棒设计，带中断-Rod shook nisoII soft-core-based design, with interrupt
ise_tutorial_ug695
- 非常有用的数字电路设计用书，也很适合初学者-useful for digital circuit design
rs_jianhua
- 实现rs编码器，用于基带信号的编码和解码，纠错编码-useful for digital siginal rs coding
jishuqi
- Verilog实现计数器功能，开发环境是Quartus-I dont know