资源列表
Mojo-FSM
- Finit state machine proce-Finit state machine process
sell-machine
- verilog sell machine 通过robei和vivado设计的建议xilinx测试程序，有助于学习vivado和fpga-verilog vivado xilinx
fenpin
- 对m序列进行2ASK调制 包含分频器 m序列发生器 正弦信号发生器 二路选择器4个模块-process m sequence with 2Ask includes frequency divider, m sequence generator, sine signal generator and MUX
ppv2
- pipeline流水线用MIPS实现，用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
cf_ad9129_ebz_edk_14_4_2013_03_12.tar
- FPGA+DDS+DAC,ADI参考设计-verification of AD9129-EVB based on FPGA
shumaguan
- 七段数码管驱动，在DE2开发板上通过拨动开关输入数字，在数码管中显示-Seven-segment LED driver, the DE2 board to enter numbers by toggle switch in the digital tube display
step_motor_fenpin
- 步进电机驱动，采用Verilog语言分频法设计，可实现一直转动。-Stepper motor drive, using Verilog language crossover method designed to achieve has been rotated.
DA_TLC5615s-Voltage-on-Digital-tube
- 使用10位串行DA芯片TLC5615将数字信号转换为模拟信号，开发板DA芯片VDD=5V,VREF=3.3V 计算公式：Vout=VREF*(N/1024) N为10位二进制码 最后使用开发板上AD芯片TLC549将电压显示于数码管上-use 10 serial DA TLC5615 and display on digital tube
DA_TLC5615_breath-led
- 使用10位串行DA芯片TLC5615将数字信号转换为模拟信号，开发板DA芯片VDD=5V,VREF=3.3V 计算公式：Vout=VREF*(N/1024) N为10位二进制码 ** 操作过程：根据需求，在程序改变10位二进制数，在DA芯片的Vout脚输出相应电压-breath led
ZZ
- 基于VHDL硬件描述语言，对CPSK调制的信号进行解调-cpsk feichanghaoyong nizijimanmankan
test
- 基于FPGA的数字秒表（数码管扫描）程序。 平台：quartusII 15.0-FPGA-based digital stopwatch (digital scan) program. Platform: quartusII 15.0
FIFO
- 该代码为FIFO代码，编译环境为Quartus/Xilinx,语言为VerilogHDL-The code for the FIFO code, compile environment Quartus/Xilinx, language VerilogHDL