资源列表
Seven_Segment_LED
- numato labs code , in verilog or in vhdl , which is very useful for small projects
UART
- UART Package Declaration with Receiver Transmitter !
gen_div
- 通用偶数分频器，通过输入频率较高的时钟信号，在设置分频参数后，得到较低频率的时钟信号。-gen div
ps2_keyboard
- vhdl for ps2 keyword vhdl for ps2 keyword -vhdl for ps2 keywordvhdl for ps2 keyword
ps2_mouse
- VHDL ps2接口 实现 鼠标传输 时序逻辑， 串口连接-vhdl for mouse(ps2)
VGA_rom_27704167
- vhdl (ps2接口） 实现rom 读取 -vhdl (ps2） for rom
VGA
- 时序逻辑 VHDL 实现VGA显示接口 串口连接-vhdl vga
dds
- 在quartus软件上，采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
HDL_Syn_V3.1
- 哈夫曼编码 包括synthesis优化。 Huffman encoding verilog code including synthesis optimization.-Huffman coding involves synthesis optimization. Huffman encoding verilog code including synthesis optimization.
combine
- 代码主要实现小车的红外避障以及超声波测距，进而控制点小车跟随人行走。-The main code of the car infrared obstacle avoidance and ultrasonic ranging, and then control point car to follow people walking.
test1
- 并编写机器码程序求1至100内能被4整除的全部自然数的和，验证该CPU核心的正确性。- write machine code program for 1 to 100 of all natural number can be divisible by 4 and, verify the correctness of the CPU core.
digi_clk
- Digital watch in VHDL.