资源列表
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
fifo
- FIFO FSM Implementation
RS_232_Test
- this file is a driver for rs-232 protocol. tx and rx. working for as uart protocol
sorter_block
- this is a code for a sorter block. read data a RAM and sort them. then write data in RAM-this is a code for a sorter block. read data a RAM and sort them. then write data in RAM
ALU
- Arithmetic and Logic Unit
Blocking-Nonblocking
- blocking and non blocking statement in verilog example.
cymometer
- 频率计，用于对一个未知频率的周期信号进行频率测量，在1s 内对信号周期进行计数，得到周期信号的频率。- Frequency meter, for an unknown frequency of the periodic signal frequency measurement, in 1s signal cycle counts, to obtain the frequency of the periodic signal.
FSM
- 序列检测器，采用有限状态机实现，检测特定序列“101011”- Sequence detector, finite state machine, detection of a specific sequence 101011
FSM
- 序列检测器，采用移位寄存器实现，检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011
ren_gen
- xilinx vhdl code for random number generator and prime number check. it can be used for cryptography
Asynchronous
- 异步加法计数器，采用D触发器实现的二进制计数器-Asynchronous adding counter using D flip-flop to achieve binary counter
water_led
- Verilog语言编写，在FPGA 上实现流水灯。-Verilog language to achieve water lights on the FPGA.