资源列表
uart
- 串口的实现代码，用verilog编写的，并附有仿真文件。-Serial implementation code written using verilog, together with simulation files.
sdram_mdl
- 基于SDRAM的读写调试试验，使用verilog语言编写，经过调试。-SDRAM-based literacy commissioning tests, using verilog language, through debugging.
fenpin
- 该程序是对输入时钟进行分频，这里是可以改变分频倍数的，这个是一个八分频的程序-The program is the input clock frequency, here is changing the division multiples, this is one eighth the frequency of the program
image
- 用来产生bayer彩色格式的图像测试程序，可生成彩色条纹，2tap输出-Bayer color format used to generate the image of a test program that can generate colored stripes, 2tap output
ir
- 这是一个红外遥控程序，可以遥控LED灯，数码管。语言verilog hdl-This is an infrared remote control program that can be remotely controlled LED lights, digital control. Language verilog hdl
AD9280-
- 进阶实验_15_AD[AD9280] ：采集模拟输入，电压动态显示在数码管 - 副本-Advanced Experimental _15_AD [AD9280]: acquire analog input voltage dynamic display digital tube- copy
pal_disp
- 实现模拟PAL格式数据，并打包成BT656到监视器显示，过程中完成了PAL打包BT656，乒乓操作、监视器配置控制等-PAL to BT656 package, monitor control
FFT-VHDL-source-code
- FFT的FPGA源码VHDL,代码说明在代码文件内有注释。-FPGA FFT VHDL source code
DDS-VHDL
- 数字频率计DDS的VHDL代码，有很详细的注释-the source code of DDS in VHDL
FSK-code-VHDL
- FSK的VHDL描述实现，更详尽的说明在代码注释内-FSK VHDL source code
HDB3-VHDL-code
- HDB3的VHDL语言描述，注释在文件内-HDB3 source code in VHDL
zybo_zynq_audio
- Zybo xc7z010 uation board,ssm6203音频编码器，PC端给音频输入，HPH输出口输出过滤噪音的音频，软件：xilinx vivado, vivado HLS, SDK-Zybo xc7z010 uation board, ssm6203 audio encoder, PC end to the audio input, HPH output port noise filter audio software: xilinx vivado, vivado HLS, SD