资源列表
03_key_detect_1
- 该程序为按键防抖程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for key stabilization program, the compiler environment Quartus/Xilinx, use language VerilogHDL
07_number_mod
- 该程序为数码管程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for the digital program, the compiler environment Quartus/Xilinx, use language VerilogHDL
16_buzzer
- 该程序为蜂鸣器程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for the buzzer, compiler environment for Quartus/Xilinx, use language VerilogHDL
25_lcd_system
- 该程序为lcd程序，编译环境为Quartus/Xilinx，使用语言为VerilogHDL-The program for lcd, compiler environment for Quartus/Xilinx, use language VerilogHDL
jpeg_latest.tar
- Jpeg Compressor in HDL language
mips16e.tar
- 使用verilog HDL编写的mips16e 16位cpu，按照mips16e官方说明编写-Use verilog HDL prepared mips16e 16 位 cpu, the official note has been prepared in accordance with mips16e
Elevator
- 基于Spartan-3E板的简易电梯控制，采用verilog编写，LCD1602模拟显示电梯状态-Simple elevator control on Spartan-3E board using verilog write, LCD1602 analog display lift status
plj.FPGA
- 本频率计基于CPLD/FPGA实现。 50MHZ标准频率为CPLD内部时钟信号，被测方波为信号发生器产生的方波信号，显示电路由TTL芯片及七段数码管组成的电路，自校正输出由CPLD输出已知频率的测试方波信号，可将其输入至测试端口，进行系统精度校正。 -The frequency meter based on CPLD/FPGA implementation. 50MHZ standard CPLD internal clock signal frequency, square-wave test
allcode
- Verilog Source Code Basys2 , SevenSegment and Switch LED Intraction
mips_cpu_code_Rev_0.5
- vhdl MIPS CODE , WORKING GOOD
wulian_dingwenxin_3012204216
- 基于quartus2的环境，做的认真，实现了微波炉的开关温度设置等-Quartus2 based environment, do seriously, to achieve a switching temperature microwave ovens, etc.
Main
- Sensor Project , Verilog