资源列表
uart
- USB与pc机串口通讯的程序，开发环境为quartus11.0.该源程序是仿照黑金的教程来做的。能够往串口调试助手上顺利发文件。-Pc USB and serial port communication program development environment for quartus11.0. The source is modeled black gold tutorial to do. Serial debugging assistant can go on successfully
edge
- 基于NIOS的硬件中断例程，该程序通过一个外部按键来验证一下中断凼数癿处理过程。所用的软件为quartus和nios。主要分为硬件开发及软件开发两部分。-Based on NIOS hardware interrupt routine, the program by an external button to verify that the interrupt number Taipa 癿 process. The software used for the quartus and nios.
caideng8
- 计能让一排灯（8只）自动改变显示花样的控制系统。可将实验板上的一排发光二极管作为彩灯用。控制器应有两种控制方式： ◆规则变化。变化节拍有0.5秒和0.25秒两种,交替出现,每种节拍可有8种花样,各执行一或二个周期后轮换。 彩灯变化方向有单向移动,双向移动,跳跃移动等。 ◆ 随机变化。变化花样相同，但节拍及花样的转换都随机出现。 -Total make a row of lights (8) to automatically change the display pattern
elevator_fpga
- 使用FPGA模拟的三层电梯，可以实现模拟开关门、上下行操作，通过LED灯显示电梯所在层数以及上下行状态-elevator fpga
keyboard
- 使用VHDL语言编写的可编程电子琴，可以实现演奏模式和回放模式-Using VHDL language programmable keyboard, can play mode and playback mode
VHDLkechengsheji
- VHDL的音乐播放器课程设计，相关代码和设计思路步骤都有，方便学习，参考。-VHDL music player curriculum design, the code and design steps, easy learning and reference.
xuliejiancejisuanqikongzhiqi
- VHDL序列检测器，计算器，控制器编码以及实现方法。-VHDL sequential detector, calculator, controller and its implementation method.
original-1-by-16-bit-multiplier
- 原码一位乘16位乘法器 用VerilogHDL语言实现-Original code A by 16-bit multiplier VerilogHDL language used to achieve
HWL_ASYNC_FIFO_DRAM_BA
- asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
HWL_PRBS_GEN
- Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators. PRBS. Verilog language
Verilog-HDL-basics-for-beginners
- Verilog HDL的基础知识,适合初学者阅读-Verilog HDL basics for beginners to read
dual-port-RAM
- 利用MegaWizard设计一个双端口RAM-Use MegaWizard design of a dual-port RAM