资源列表
long_training_ise10migration
- 无线通信系统长训练序列生成模块。ISE完整工程。 -Long training module for wireless telecom system.ISE full project.
short_training
- 无线通信系统短训练序列生成模块。ISE完整工程。-Short training module for wireless telecom system.ISE full project.
DATA_Pilot_Insert
- 无线通信系统导频插入模块。ISE完整工程。 -Pilot insert module for wireless telecom system.ISE full project.
RSIC_CPU
- 指令寄存器在clk上升沿把数据总线送来的指令高八位或第八为寄存器中-instruction register and it s textbench
lcd12864
- lcd12864液晶显示 Verilog语言-lcd12864 VerilogHDL
key_led
- led灯按键控制 VerilogHDL 始于FPGA入门学习-led control VerilogHDL
FIR-VHDL
- 15阶FIR滤波器的设计VHDL代码 ，包括顶层模块及各模块的VHDL设计代码-15 order FIR filter design VHDL code, including the top-level module and each module VHDL design code
81245password
- 八位密码锁的控制电路，当从拨码开关输入的八位二进制数与密码（预置八位二进制数）相等时，输出开锁信号以驱动执行机构工作，用红灯亮、绿灯熄灭表示关锁，用绿灯亮、红灯熄灭表示开锁。-Eight locks control circuit, when the DIP switch input eight binary number and password (preset bit binary number) are equal, the output signal to unlock the wor
two_ADF4350_vhdl_code
- 该程序实现：控制两个ADF4350的VHDL程序；多个选通信号的编码。-The realization of the program control: two ADF4350 VHDL program a plurality of gate signal coding.
uart_tx
- 用Verilog实现通过上位机向串口发送多帧数据，并具有抗噪功能-Implementation serial port receive more frame data by software use Verilog, and has the function of the resist noise
booth_mux4
- 基于verilog的4位booth算法编写-Written on verilog of 4 booth algorithm
my_clock01
- 用VHDL语言实现电子钟功能，用不同模块按时分秒显示-To achieve the electronic clock function with VHDL language