资源列表
ask
- 基于Quartus9开发的一个关于ASK调制和解调的仿真，顶层用原理图，各个模块使用VHDL语言编写-Quartus9 developed a simulation on ASK modulation and demodulation based on the top floor with a schematic, each module using VHDL language
TLV5619
- vhdl 实现的tlv5619模块测试程序，时序简单可行，便于移植。-this vhdl file for tlv5619，it convient to move to other place to use.
designreport
- 简易自动售货机，带led动画，可进货找零选择不同商品-Easy vending machines, with led animation, the change may choose to purchase different commodities
Decoder
- 74ls138译码器所有功能的实现，结构风格-entity of 74ls138 decoder
fft_512
- 采用Xilinx提供的VHDL FFT ip核实现512点FFT，可以实现使能控制、时钟控制等功能-Using Xilinx provides VHDL FFT ip core to achieve implementation of 512 points FFT, with enable control, clock control and other functions
CIC_filter
- 三级级联梳状滤波器（CIC）的verilog实现。顶层模块top_moduole下面包含三个子模块，积分模块integrated，抽取模块decimate和梳状滤波器模块comb，已验证可综合通过并实现CIC功能-Three-level cascade comb filter (CIC) verilog implementation.Top-level module top_moduole below contains three child module, integral module in
case-and-if-programing-in-verilog
- Case语句和if语句在电路设计中的注意事项，各种产生锁存器的原因分析，以及原代码-case and if using in verilog
cnt5_fsm
- 这是一个简单的vhdl状态机例程，适合新手学习，简单易懂。-This is a simple state machine vhdl routines, suitable for beginners to learn, easy to understand.
DFF12
- 简单modelsim testbench测试工程，包含源码和testbench文件-Modelsim testbench simple test project, including source code and testbench files
uart_tx
- 带有奇偶校验功能的的串口发送模块，实现uart功能。verilog硬件描述语言实现-With the function of parity of serial port to send module, uart functions.Verilog hardware descr iption language to realize
init_LCD
- Initializes Toppoly TD043MTEA1 LCD. R02: Type 1 Dot inversion, VD and HD low polarity, Latch data on falling edge, 800x480RGB R03: Software register standby, pre-charge enabled, 100 drive capacity, PWM enabled, VGL pump enabled, cp_clk enabled, n
qsys2014
- 介绍qsys的使用，是基于quartus13.0版本的操作，比较好的一本教程-Introduced the use of qsys, is a version of the quartus13.0 based operation, a good tutorial