资源列表
entrelacement-vhdl
- VHDL Implementation Interleaver
verilog
- vivado的led灯的学习程序，有兴趣学习soc的可以下载-the program for vivado study on SOC
FPGA--uart
- FPGA串口通信源码,通过Verilog来实现功能，新手可以参考下-FPGA uart
FPGA--example
- 一些有价值的FPGA例子，大家可以参考一下。VHDL-fpga example
LPC post
- 使用VHDL语言通过LPC接口实现的post卡功能，用于debug
counterdiv
- 用D触发器组成2分频电路，并对时钟进行计数-2-div frequency using D flip-flop circuit.
EX3_LED
- 完成LED的自加功能，里面包含完整的说明和测试文件-Complete self-plus-function LED, which contains complete instructions and test files
EX4-DA_TLC5615
- 主要实现AD转换模块的驱动，包括AD的测试模块。-The main driver to achieve AD conversion module, including AD test modules
EX7_BINARY2GRAY
- 本模块是实现格雷码和二进制码的转换，并给出仿真测试文件-This module is to achieve the conversion of Gray code and binary code, and give the simulation test file
antenna-effect
- 硬件电路设计中消除天线效应的电路RTL级Verilog代码-RTL grade of Verilog codes for reducing antenna effect
RAM_Delay
- 利用块RAM实现数据延时，ab两路数据的位宽都是32位，a路延时16个时钟，b路延时8个时钟-Using block RAM data latency, ab two way data bits wide is 32, a way to delay 16 clock, eight clock delay b road
LED
- 控制LED灯显示 滑动开关0往上时红色LED0会亮 滑动开关1往上时红色LED1会亮 滑动开关0与1在相同状态红色LED2会亮 滑动开关0与1皆往上红色LED3会亮 -Control LED lights display the slide switch to 0 will light up red LED0 1 slide switch will light up red LED1 slide switch between 0 and 1 in the same state wil