资源列表
universal
- vhdl code of universal shift register which o/p is control by mode input
24bitdivderVerilog
- FPGA 24位除法器编程,verilogHDL编程-The 24 bit divder used in FPGA，programmed in verilog HDL.
vga
- VGA project for DE0-nano
conv
- Convolution using VHDL (pls don try this)
Ch
- design of cache to remove tag bits
manfm
- Manchesteer-FM0 coding using verilog
dd
- Digital Delay using Verilog (The program is wrrong I ll upload the right one soon)
dsp
- DSP Architechture using Verilog. (the concept of the programm differ the original)-DSP Architechture using Verilog. (the concept of the programm differ the original)
agc_gen
- AGC(自动增益放大) Verilog代码 设计可以参考-AGC (automatic gain control) can refer to the Verilog code design
agc_gen2
- AGC(自动增益放大) Verilog代码 设计可以参考 第二部分-AGC (automatic gain control) can refer to the Verilog code design
Affichage_VGA
- Display image via VGA port in FPGA bord
FPGA-Implementation
- Interleaving with error correction