资源列表
small8
- This a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA. -This is a sample microprocessor with a bi-directional data bus and RAM in software created in VHDL run on a cyclone 3 FPGA.
4bit-microprocessor
- This file is 4bit microprocessor that included a variety of modules like ALU,Progrem Counter and ACC etc It is to calculate 4bit binary Topblock is top level module.
car
- 基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码，用Verilog语言，传感器有红外传感器以及超声波传感器-Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors
EP2C5T144_VGA
- VGA EP2C5T altera QuartusII VHDL FPGA CPLD passed
PEX8311_test
- PEX 8311 OK PCI e cycloneIII altera quartus FPGA CPLD
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
S1_38yima_NEW
- 本次实验主要实现一个 3/8 译码器,在本实验的程序中是由 SW1、 SW2、 SW3 分别对应三位的二进制。 SW3 SW2 SW1 ： 所对应数字及二极管 0 0 0 ： 0 DD1 0 0 1 ： 1 DD2 0 1 0 ： 2 DD3 0 1 1 ： 3 DD4 1 0 0 ： 4 DD5 1 0 1 ： 5 DD6 1 1 0 ： 6 DD7 1 1 1 ： 7 DD8-This experiment mainly to achie
S2_counter_NEW
- 设计一个以十进制为基础的计数器，实现从 0 开始的计数功能；本实验主要是利用开发板上面的数码管实现一个十进制计数器的功能，计数范围0000-9999，可实现循环计数。先输入verilog 程序，然后在 QuartusII 中做波形仿真，通过后下载程序在数码管上查看计数器的功能。-Designing a decimal-based counters, a zero-counting function this experiment is the use of digital control b
S3_SW_PB_NEW
- 设计一个通过按键（ PD)和拨码开关（ SW）来控制 LED 灯的实验 本实验是利用底板上的按键及拨码开关来实现对 LED 灯的控制，其中对应关系为SW1—SW6 分别对应 DD1—DD6，PD1—PD8 分别对应 DD1—DD8。-Design is controlled by a key (PD) and a DIP switch (SW) LED lamp experiment this experiment is the use of keys and the DIP switch o
vga
- vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a
add
- The circuit 1 in is a 1-bit binary adder with 3 inputs (A, B and Carry-In) and 2 outputs (Sum and Carry-Out).The circuit 2 depends on circuit 1 which create a VHDL file ADD4 which is a 4-bit binary adder built using ADD1 components.
sayeh
- The SAYEH (Simple Architecture, Yet Enough Hardware) is a processor architecture that has been developed by Navabi in [1] for experimental and teaching purposes. As the name implies it is a “simple” architecture but contains sufficient hardware to ma