资源列表
adc0804_new.rar
- AD0804驱动，使用新的查表方式，可大大的降低数值运算，节省CPLD的资源,AD0804 driver，using a new method_look up table,which can save a lot of resources of CPLD
fifo_32_4321.rar
- 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench,Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
xapp1076
- Implementing Triple-Rate SDI with Spartan-6 FPGA GTP Transceivers
DAY07
- verilog 编写的查询法和线反转法举证键盘实例程序-verilog matrix—key
MySDTEST
- 读取F16文件系统的SD卡里面的bmp文件-To read bmp file of F16 file system on SD card
uartfifo
- 串口收发程序，VHDL版本，适用于ALTERA的CPLD -Serial transceiver procedures, VHDL version
lanqiu24s8
- 篮球24s计时。计时器递减计数到零时，数码显示器显示‘0’并停止，同时发出报警信号-basketball 24 seconds
ml506_lab_resources.zip
- xilinx 开发板ML506 示例代码集合。,Xilinx ML506 development board sample code collection.
cordicDDS
- Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
USB2UART
- usb串口通信的固件程序与FPGA控制程序-usb serial communication firmware and FPGA control program
vhdl语言实现的16乘16的点阵显示设计代码
- vhdl语言实现的16乘16的点阵显示设计代码，调试通过，可借鉴-VHDL language to achieve the 16 by 16 dot matrix display design code, debug is passed, can learn from-vhdl language implementation of the 16 by 16 dot matrix display design code, debug through, we may learn-VHDL langu
FPGA-digital-clock-design
- 运用顶层设计思路设计好各个底层文件（VHDL代码），对各个底层文件进行功能仿真；采用原理图或者文本方法来实现顶层文件的设计，对顶层文件进行功能真仿真。在顶层文件功能仿真正确之后，把顶层文件下载到实验箱的FPGA里边去，验证电路功能是否正确。具体时间用6位数码管来显示，具有整点报时功能. -Designed various underlying file using top level design (VHDL code), on functional simulation of variou