资源列表
024-DAC902
- verilog控制dac902的程序，先从fifo读取数据-the verilog control the dac902 procedures start fifo read data
022-FIFO_PRO
- verilog写的控制quartus自带fifo ip核的程序-verilog to write the control quartus own fifo ip nuclear program
rgb2yvu
- rgb转为 yvu的四种实现方法 verilog-four methods for rgb converted to yvu
ROM_RTL
- Verilog Source File In the Quartus10.0 can be run this source code.
clock
- 实现FPGA的数字钟的实现，具有小时、分、秒等功能-FPGA digital clock, with hour, minutes, seconds and other functions
seg70_ise7_bak
- 7SEGMENT VHDL CODE-THIS CODE VERY GOD FOR DRIVE 7SEG-IN ISE FUNDATION 11.1
buzz_ise9migration
- TISH PROGRAM VHDL CODE -THHIS CODE GOD FOR DRIVE BUZER IN ISE
I2C_ise7_bak
- Uncomment the following library declaration if instantiating any Xilinx primitives in this code. library UNISIM use UNISIM.VComponents.all I2C DRIVE IN VHDL
lcd1602_ise7_bak
- THIS CODE VERY GOD FOR DRIVE LCD2X16 THISE CODE IS TESTED CRYSTAL 40MHZ RESET VERY IMPORTANT KEY IN THIS PROGRAM
ps2_ise7_bak
- THIS CODE VERY GOD FOR DRIVE PS2 THISE CODE IS TESTED CRYSTAL 40MHZ RESET VERY IMPORTANT KEY IN THIS PROGRAM
UART
- IM DESINING VHDL COD EIN IS THIS CODE IS GOD AND TESTIN VERY GOOD
VGA
- THIS CODE VERY GOD FOR DRIVE VGA IN CRT MONITOR WITH CPLD AND FPGA