资源列表
RISC-CPU-design
- 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the thre
20120720
- 北京大学信息科学技术学院开设的2012暑期课课程—基于FPGA上的VHDL设计，内容包含全部必选实验的工程文件和仿真波形。-Opened the 2012 Summer Course in Science, Peking University Institute of Technology- based on the FPGA VHDL design, the project file that contains all mandatory experiments and simulation
verilog-fir
- 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
DATA_SAMPLE
- 运用VHDL实现双时钟沿的数据采集（上升沿和下降沿同时采集）-The use of VHDL data acquisition (rising and falling edges of the dual clock edge Acquisition)
niosii_study
- 学习NIOSII时自己下载总结的资料，拿出来大家一起分享-In learning NIOSII to download the summary of the information out to share with everyone
LED_driver
- LED灯光驱动的概念以及实现方法，可以作为对比，实现自己想要的驱动电路-Concept and the implementation of the LED light-driven, can be used as a contrast, they want the drive circuit
sdram_test
- 自己实现的一个基于SOPC架构的SDRAM模块-Own implementation of an architecture based on SOPC SDRAM module
LedCube
- LedCube for students.
vhdl
- vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。-vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.
Block1_restored
- 使用VHDL写的I2C通信模块，这个模块包括和单片机通信的部分和24C16通信的的部分-Use VHDL to write I2C communication module, this module include the single-chip communications to and 24C16 communication of part of
FPGA_TOP_ForYaoQi
- 分频器：利用计数来实现25M分频成10M的时钟，并且在开发板上利用LED实现跑马灯。-Divider: the use of the count clock frequency into 10M 25M points, and in the development of on-board LED to achieve the Marquee.
diff_coding
- 在通信系统中，需要进行各种调制，比方说bdpsk，而该调制需要进行差分编码-bdpsk differential，to peap the modulation