资源列表
clock_2
- verilog hdl 时钟程序，数码管显示，并可设置闹钟-verilog hdl clock program, the digital display, and can set the alarm
decoder_38
- 38译码器，用verilog hdl 编写-38 decoder, written in verilog hdl
code
- this a vhdl code for ofdm modulator and can be implemented using fpga-this is a vhdl code for ofdm modulator and can be implemented using fpga
7113
- SAA7113芯片初始化配置程序，主要功能：把1路模拟视频信号输入转化为8路656格式的数字信号输出-The SAA7113 chip initialization configuration program, the main function: an analog video signal input is converted to 656 format of the 8-channel digital signal output
Success
- 视频解码芯片SAA7113和视频编码芯片SAA7121初始化配置，一路模拟视频信号从SAA7113输入，转换为数字信号，然后SAA7121把数字信号转化为模拟信号输出-Video decoding chip SAA7113 video encoder chip SAA7121 initial configuration, all the way analog video signal from the SAA7113 input, converted to digital signals, th
sram_5_successed
- 存储器SRAM读写程序，将数字信号存入SRAM-Memory SRAM read and write procedures, the digital signal into the SRAM
Xilinx-verilog
- xilinx培训源码及工程文件,给予spartan 3E开发板的！希望对初学者有所帮助-Xilinx training codes and project！！ IT‘s worth to learn！！
verilog-code
- verilog代码实例，大量的代码文件对设计文件很好-to many verilog code for design
sanjiaobo
- 三角波生成 和 正弦的 vhdl的语言编写-The preparation of the triangle wave generation and sinusoidal VHDL language
Buttons-control-the-digital-tubes
- 在FPGA开发板上用verilog语言实现，多按键控制四位数码管，显示不同的数字。-FPGA development board with verilog language, multi-button control of four digits, show different figures.
Buttons-control-the-output-waveform
- 在FPGA开发板上，利用verilog语言，实现按键控制输出波形的参数值，并且在数码管上显示相应参数。-On the FPGA development board, use the verilog language to achieve the function that use the button to control parameter values of the output waveform and display them on the digital tubes.
sim
- 时钟倍频后，通过Modelsim仿真验证任意占空比可调的PWM信号-After the clock multiplier, through Modelsim simulation arbitrary variable duty cycle PWM signal