资源列表
de0_epcs_led
- de0的 采用epcs sdram 搭建的最小系统点亮led等-de0 with epcs the sdram to build the smallest and the system light led
TASK51_DE0
- FPGA内嵌51核，已通过调试及下载验证。-FPGA embedded 51-core, debug and download validation.
led7219
- MAX7219驱动程序，应用于cyclone 1c12，电子设计大赛使用过的-MAX7219 driver, used in the cyclone 1c12 used by the Electronic Design Contest
直方图统计的Verilog实现
- chengxu:直方图统计的Verilog实现，大家可以共同学习
eetop.cn_Crack_Modelsim.SE.6.6
- Modelsim 6.6c keygen
Altera Modesim破解版的LICENCE
- Altera Modesim破解版的LICENCE. 下载解压后: 1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行). 2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt" 3.搞定,Altera Modesim cracked version of the LICENCE.
用verilog编写的液晶显示程序
- 用verilog编写的液晶显示程序，已调试通过。 1、 本工程主要是设计一个LCD的控制模块，然后在LCD上显示想要显示的数据。 2、 通过JTAG口把LCD12864.sof下载到FPGA上，则LCD就会显示出要显示的数据。-Written liquid crystal display with verilog program has been through debugging. 1, this project is to design a LCD control module, a
Altera Quartus II 10.1最新破解文件
- Altera Quartus II 10.1最新破解文件，本人一直独家专用，X86和X64都有。-Altera Quartus II 10.1 latest crack file, I have been exclusively dedicated, X86 and X64 have.
FLASH存储器的读写程序
- 此源码为基于FPGA的使用VERILOG编写的FLASH存储器的读写程序。,The source code for the FPGA-based FLASH memory using the VERILOG prepared to read and write procedures.
用assign 语句描述的三态门
- 用assign 语句描述的三态门，三态双向驱动器，3-8 译码器，8-3 优先编码器等等,With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
RS232串口通信协议
- RS232串口通信协议，verilog实现，通过FPGA完全调通。,RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.