资源列表
send_test
- 输入时钟，可以得到周期性的有效信号以及同步信号，同时可以随时钟输出8个字节的数据-Input clock, can be an effective signal, as well as periodic synchronization signal, at the same time can be 8-byte clock output data
testproject2
- 利用VHDL编写的counter程序，基于FLIP-FLOP-Counter the use of VHDL procedures prepared, based on the FLIP-FLOP
8051
- 8051单片机VHDL内核,内有说明,很详细,值得下载-8051 VHDL core, which has made it clear that, in great detail, it is worth downloading
mc8051
- mc8051内核,VHDL程序,内有说明,超详细.-mc8051 kernel, VHDL program, which has made it clear, super-detailed.
usb_funct
- VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
pwm
- 实现PWM波型....使用VHDL语言-Realization of PWM waveform using the VHDL language ....
counter10
- 带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
100vhdl
- VHDL常用实例，适合初学者，有计时器等常用例子-Common examples of VHDL, suitable for beginners, there are examples of commonly used timer, etc.
DCT
- 用于视频图像编码的8×8DCT变换，可用于MPEG4.H263等VHDL编程-For video images encoded 8 × 8DCT transform, can be used to MPEG4.H263 such as VHDL Programming
Huffman
- 用于视频运动图像编码的HUFFMAN编码，可广泛运用于MPEG-Moving Picture for video coding Huffman coding, can be widely applied to MPEG
VGADIY
- 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
FPGAPROGRAMCHAPTER6
- FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节，然后把它接收回来。 -FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.