资源列表
MUX
- VHDL code for MUltiplexer
ALU
- VHDL code for 3 bit ALU
Yeni_klasr
- 8 bit Insruction register
all_cpu_scheduling
- the program gives cpu scheduling implementation
seg71
- ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０--7 实验的目的是向用户介绍多个数码管动态显示的方法。 动态显示的方法是，按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段。-7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to th
iic
- 跑马灯实验：利用计数器轮流点亮LED灯，实现各种动态效果。-Marquee experiment: the use of counter rotating light LED lights, to achieve a variety of dynamic effects.
RS_decode
- RS（204,188）译码，verlilog硬件描述语言的实现-rs decode
AND
- vhdl code for AND gate
XOR
- vhdl code for XOR gate
FPGA_CLB
- FPGA可编程逻辑模块CLB的设计，pdf格式，希望对大家有帮助-FPGA programmable logic block CLB design, pdf format, we hope to help
ISE_guide
- ISE使用指导，简单介绍了ISE的开发流程，pdf格式，希望对大家有帮助-ISE to use the guide, a brief introduction of the ISE' s development process, pdf format, we hope to help
vga_principle
- vga显示原理与vga时序实现，doc格式，希望对大家有所帮助-vga vga display timing and realization of the principle, doc format, we hope to help