资源列表
checkoutthedate
- 该程序的功能是用来查询日期或是知道日期查询星期几的；-The program' s function is used to check the date or the date of check to know a few of weeks
arithmeticdesigntoverilog
- VHDL语言经典的22个编程实例，对初学者很有帮助。-VHDL language classic 22 programming examples helpful for beginners.
gateclockexcursionanalysis
- 门控时钟与时钟偏移分析，详解门控时钟偏移的产生和解决办法。-Gated clock and clock skew analysis Xiangjie gated clock skew of the generation and solution.
CPLDFPGA
- EDA工具应用丛书_CPLDFPGA的开发与应用
VerilogHDL
- 适合于硬件描述语言的入门学习资料 强烈推荐适合于已经有一定的语言基础-Hardware descr iption language suitable for entry-learning materials has been strongly recommended for a certain language-based
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
cic_intp_64_four
- 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
11orderFIR
- 11阶FIR数字滤波器，Verilog版本，数字下变频，适合初学-11-order FIR digital filter, Verilog version of the digital down conversion, suitable for beginners
pinlvji
- 数字频率计的Verilog HDL语言实现，已经通过仿真-Digital frequency meter Verilog HDL language implementation has been through simulation
frequency_counter
- 数字频率计的FPGA设计与仿真，VHDL版本，适合初学-Digital frequency meter for FPGA Design and Simulation, VHDL version, suitable for beginners
v16forlcdfpgaconnection.tar
- its a source code and the entire project package for connecting to fpga
VHDLonfir
- FIR滤波器在VHDL中使用(顺序)PROCESS声明或者是加法器和乘法器的“组件 实例”来实现-FIR filter in VHDL use (in order) PROCESS statement or the adder and the multiplier " component instance" to achieve the