资源列表
CPU
- CPU的构造，采用veril语言 对计算机专业同学有用-CPU
polyphase
- The current portion of the collaboration has involved the feasibilty and implementation of a Polyphase Filter bank using various FPGAs and hardware architectures
AD6635
- The AD6635 is a multimode, 8-channel, digital Receive Signal Processor (RSP) capable of processing up to four WCDMA channels
ip_digifrec
- The Digital IF Receiver megafunction combines a quadrature NCO and a digital mixer to translate the input IF signal down to baseband
prog_dds
- FPGA VHDL DDS程序，采用FPGA实现1hz到100khz可调的dds程序，频率调节步长是变化的。-FPGA VHDL DDS program, using FPGA to achieve 1hz to 100khz adjustable dds procedures, the frequency adjustment step size is changing.
seven
- 基于VHDL实现输入控制7段数码管的代码，分别用逻辑表达式法和真值表法实现。-VHDL-based implementation of digital control input control 7-segment code, respectively, a logical expression method and truth table method to achieve.
MUX
- source s file of multiplexor
serialports2
- 使用verilog以及VHDL编写的将串口数据转换为32位并口数据，作为FPGA和DSP接口使用（DSP型号：6205）-Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
PROCEDURETOWORKINISE
- Procedure to Work in VHDL... by Ashok Kumar . A . M Zebros India
BASICVHDLCODES
- BASIC VHDL DOCUMENTS BY ASHOK KUMAR.A.M ZEBROS INDIA
2005-12-29_22-34-9_93
- bench verilog 源代码，适用于图像开发-bench verilog source code, apply to the image development
verilogdct
- dct实现verilog hdl的数字图像处理，源代码-dct achieve verilog hdl digital image processing, source code