资源列表
MII
- 这个很简单，但是很全面的网路资料，大家快看看哦。-This is simple, but very comprehensive network of information, we quickly take a look oh.
uart_tx
- this code is in VERILOG HDL .. its for serial communication ..it allows serial data transmission from FPGA to computer
FIFO
- 该FIFO应当提供用户读使能和写使能输入控制信号，并输出指示FIFO状态的非空和非满信号，FIFO的输入、输出数据使各自的数据总线：in_data和out_data。-The FIFO should be provided to enable users to read and write enable input control signal, and outputs instructions FIFO status signals of non-empty and non-full, FIF
alu32bit
- alu逻辑运算单元的源码，可方便交流和学习-alu ALU source code, can easily exchange and learning
mipsfinal
- 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
usb_model
- usb接口model原码设计,可以模拟USB的接口数据接收,用于usb接口数据的仿真.-usb interface model of the original codes designed to simulate USB interface data reception, usb interface data for the simulation.
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
SLAVE_FIFO_16BITS
- 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
lowpassfir
- Low pass fir filter for ecg signal in VHDL
RS_ENCODER
- DVBC RS编码,标准TS流输入输出接口!-DVBC RS encoder
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
asi_framesync
- 从串行TS流中找到同步头,生成标准并行TS流的方法!-Be found in TS stream from the serial sync header to generate the standard method of parallel TS stream!