资源列表
4_bit_counter
- 4 bit counter with vhdl code
Stopwatch
- 这个设计是电子科技大学集成电路综合课程实验的项目，主要内容是跑表-This design is the University of Electronic Science and Technology Experiment IC integrated curriculum project, the main contents of stopwatch
fir_1
- 这个FIR滤波器是基于ALU框架编写的，仅供参考使用-The FIR filter is based on the framework of the preparation of ALU, the only reference to the use of
2.CLK1HZ
- make 1hz clk, using xc95144 CLPD
thesis_all
- VHDl code for USB microcontrolel
DSPHBControl
- DSP Example Code for programming an Hybrid AC/DC converter-DSP Example Code for programming an Hybrid AC/DC converter
Verilog_uart
- UART communication code
fifo
- 很多关于FIFO的文章其实讨论的都是空/满标志的不同算法问题。 在Vijay A. Nebhrajani的《异步FIFO结构》一文中，作者提出了两个关于FIFO空/满标志的算法。 -FIFO FULL/EMPTY Arithmetic
quartus_warning_analysis
- Quartus常见警告分析，中英文注释，非常实用的资料。-Quartus warning and errors analysis
QutartusII_compatibility
- 关于Qutartus II 器件垂直移植（兼容设计）方法-Qutartus II devices on the vertical transfer (compatible design) method
Verilog-HDL
- 《北航常晓明Verilog应用》一书的pdf完整版，是学习Verilog的好书-" Beihang Chang Xiaoming Verilog Applications" pdf full version of the book is a good book to learn Verilog
Xilinx_Tutorial
- XILINX FPGA TUTORIALS PDF FILE