资源列表
Decoder
- the decoder program are used to decode the data for 4:1 decoder using xilinix
encoder
- the encoder are designed to two for switchcase and if else function in verilog
mux
- the multiplexer program are designed 2:1 and 4:1 in verilog model
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
signaltapdebugging
- FPGA 逻辑分析仪signaltapII详细用法介绍与调试分析-FPGA signaltapII design and debugging
eth_ocm_80_3
- MAC ethernet ip opencore
system_c_code
- Counter , adder , reset code using system c
bram_test
- Hex file to Binary file conversion using VHDL
round_three_stage
- 3 stage round arbiter using verilog
qpsk_simulink
- Matlab simulink qpsk
speed_test
- QuartusII运行环境下的计数器的VHDL源代码，其中有部分文档说明。-QuartusII operating environment under the counter VHDL source code, some of them documented.
spartan-3E
- xilinx公司的FPGA的spartan-3E系列套片参数手册-xilinx the company' s FPGA-spartan-3E series of set piece argument Handbook