资源列表
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
sqrt_LUT8
- Square root calculation: S=N^2+d using LUT-Square root calculation: S=N^2+d using LUT
fifobaseddprammemory
- This file if about DPram based fifo storage... wirte and read in both ports
DP_RAM.v
- tis about dpram... if u have any quries fell free to ask -tis is about dpram... if u have any quries fell free to ask
flowvhdl
- 16 bit adder source code.
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
memory
- the memory program are used to design the fpga application for in very log module
registers
- in this coding are used to realize the synties and beherival modeling in vhdl
statemechine
- We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine f
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
acum_hdl
- phase accumolator in vhdl & test bench for it for dds-phase accumolator in vhdl & test bench for it for dds