资源列表
erjielvbq
- 使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过-Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter descr iption has been run through
10_ps2_keyboard_test
- FPGA通过ps2接收键盘数据，然后把接收到的字母A到Z键值转换相应的ASII码，通过串口发送到PC机上。 实验时，需要接键盘，还要用调试助手，下载程序后，在键盘上按下一个键，比如A，则在PC调试助手上可看到A -Through FPGA receive the ps2 keyboard data, and then receive the letters from A to Z key value into corresponding ASII code, through A seri
ADC
- 利用状态机实现对TLC549的采样控制，实验时可调节电位器RW1（在开发板底板左下角），改变ADC的模拟量输入值，数据采集读取后在数码管上显示。-Using state machine implementation of eight bits sampling control, adjustable potentiometer RW1 experiments in development board (bottom left corner), change the ADC analog inpu
1123212
- 用VHDL写的一个数字时钟程序，调试成功-Use VHDL to write a digital clock procedures, debugging success
taxi_cnt
- 出租车计费器 根据出租车计费器原理本逻辑模块需包括以下内容：复位模块，开始计费模块，里程计数模块，里程判断模块，停车判断模块，停车计时模块，停车时间计费模块，里程计费模块，总计费模块，LED计时里程计费显示模块，高额费用报警；-taxi count
mouse_vga_2.0
- 基于CycloneIII FPGA开发的PS2鼠标和VGA接口逻辑，采用Verilog编写。-CycloneIII FPGA-based development of the PS2 mouse and VGA interface logic, using Verilog.
LBC_Avalon2.0_SOPC
- 基于SOPC Builder, EP3C40系列FPGA的Avalon总线和MPC8349处理器本地总线LBC，采用Verilog编写的Avalon总线与LBC的转换接口。-Based on SOPC Builder, EP3C40 FPGA family Avalon bus and MPC8349 Processor Local Bus LBC, using Verilog prepared with LBC conversion Avalon bus interface.
PPC_VME-2.0
- 基于PowerPC和FPGA开发的VME控制器的VME接口，采用SOPC建立环境，利用Verilog开发了接口时序。-PowerPC-based and FPGA development VME VME controller interface, using SOPC build environment, the use of Verilog developed interface timing.
VGA
- verilog编写的VGA 2选1切换 经验证，正确-verilog prepared VGA 2-to-1 switching proven correct
divider_with_cache
- 带缓存的除法器,包括test bench，在普通除法器上加上缓存功能-divider with cache
DES
- 该源码采用DES加密标准，采用Verilog编写，时钟为50M，可以扩展为硬件级加密系统-The source uses DES encryption standard, Verilog prepared, the clock is 50M, can be extended to hardware-level encryption system
fwPVerlilog
- 68013与FPGA的通信，包含了固件程序与verilog程序-68013 and FPGA communication, including firmware and verilog program