资源列表
DDS_8bit_5_7yigai
- DDS函数信号发生,基于fpga的DDS函数信号发生器，已在黑金版上验证。-DDS Function happen fpga-based DDS Function Generator has been verified on the black gold version.
music-playing-hardware-circuit
- 使用quartus6.0编写的乐曲硬件演奏电路（选项中没那个软件，所以在这儿注释了）通过按键实现简易音乐的通过蜂鸣器播放。具体的引脚定义这里不好多说什么，选择的芯片不同，引脚锁定也不同，这边用的芯片EP2C6Q240C8-Use quartus6.0 write music playing hardware circuit (option not that software, so here annotated) through the keys to achieve simple music
8051Core
- 这是个基于FPGA的IP核型MCS51单片机+频率计设计实验。-This is a type of FPGA-based IP core MCS51 MCU+ frequency meter design experiments.
AD0809-sampling-RS232
- 这是个AD0809信号采集与频谱分析电路设计，里面包含RS232接口通信状态机，LPM-RAM数据缓冲，A/D采样控制状态机，RS232通信适配电路。-This is an AD0809 signal acquisition and spectrum analysis circuit design, which includes RS232 interface communication state machine, LPM-RAM data buffering, A/D sampling co
AD0809_MOTO
- 这是个ADC采样控制状态机设计及电机控制设计。-This is the ADC sampling control state machine design and motor control designs.
div2
- 一种触发器电路的实现方案，效果还可以。速度也比较快。经过方针验证，可以运行。-One kind of flip-flop circuit implementations, the effect can be. Speed 椠猀 relatively fast. After verification guidelines, you can run.
V-6-FPGA-Configure-Guide
- Xilinx公司的Virtex-6配置指南，是详细的官方指南-Virtex-6 configuration guide Xilinx company, is the official guide
zhongji
- 基于vhdl的dds信号发生器程序，具有一致十k调频功能，输出32k及64k正弦波-Based on the dds signal generator vhdl program has a consistent ten k FM function, 32k and 64k sine wave output
uart
- RS232串口的应用实例，其中用到了FIFO-RS232 serial port application, which uses a FIFO
juanji_3_3
- 自己写的3*3的高斯卷积模板，用Verilog在ISE上写的-Write your own 3x3 Gaussian convolution mask, using Verilog write on the ISE
sig_control
- 交通信号灯的verilog实现，里面包含有源程序和仿真图。-Verilog realize traffic lights, which contains the source code and simulation diagram.
wled
- verilog流水灯设计开发,已经经过验证的。-verilog water lamp design and development, has been proven.