资源列表
Manchester
- 实现Manchester的编码和解码功能，基于Lattice FPGA完成仿真，验证代的正确性-Implementation of Manchester encoding and decoding function, based on Lattice FPGA complete the simulation to verify the correctness of generations
mcbsp_1_14
- DSP的McBsp接口的实现，不过是作为DSP的从机-The realization of McBsp interface of DSP,But the Base is the FPGA as a slaver.
RD1025_rev01.1
- ECC纠错技术，可以对数据中出错的一位进行自动纠错，基于Lattice FPGA实现仿真测试-ECC error correction technology, the data in an automatic error correction, Lattice FPGA-based realization of simulation test
final_system
- verilog实现串口收发，发送本人的学号哈，可以拿来参考一下的，电子科技大学数字设计课程。-Serial transceiver verilog send my student number Ha, can be used to refer to, electronic, digital design courses University of Technology.
mclock
- 电子时钟设计 包含校时和闹钟功能 闹钟播放一段音乐 ppt和word报告也有 太大不上传 需要的发邮箱lin170587788@gmail.com-Electronic clock and alarm functions including school play a musical alarm clock ppt and word report also does not upload much needed hair mailbox lin170587788@gmail.com
music_player
- 音乐播放器： 1.可以播放四首乐曲，设置play、next、reset三个按键。按play键播放当前音乐，按next键播放下一首音乐。 2、LED指示播放情况（播放时点亮）、LED2和LED3指示当前乐曲序号。-Music Player: 1. Can play four songs, set the play, next, reset three buttons. Press PLAY to play this music, press the next button to play
Lee-Sa-Ru-graphics-implementation
- FPGA 用virlog语言实现李萨茹图形的变化，包括调相，调频等功能。-FPGA using virlog language Lissajous Ru graphic changes, including phase modulation, frequency modulation.
cam_cap_fpga
- 包含上位机源代码，电路板的FPGA源码，实现摄像头的捕捉和采集-PC contains the source code, circuit board FPGA source code, achieving camera capture and collection
RiscCpu
- 这是根据夏宇闻老师的书编写的一个risc_cpu源码，包括很好的测试文件-This is according to Xia Wen teacher' s book written in a risc_cpu source, including good test file
fir_filter_50Mhz
- 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
VGA_interface
- 采用FPGA控制VGA的借口，采用Verilog编写，Quartus II编译，恰当配置后开发板可以与显示器相连显示图像-Using FPGA to control VGA excuse, Verilog prepared, Quartus II compilation, the proper development board can be configured to display an image attached to the monitor
IIR
- 使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过-Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter descr iption has been run through