资源列表
cordic
- 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
shuzi
- 讲述了全数字信号发生器部分频率值测算的表格-Full digital signal generator frequency value calculation form
VHDL
- VHDL功能模块直接用。分有： 去抖，数码显示，任意分频。-VHDL modules directly. Points are: to shake, digital display, arbitrary frequency.
apb_i2c
- Simple realization of I2C interface on System Verilog HDL with support of interrupt generation.
Ldpc_DecodeV1
- block-LDPC 译码VHDL 源代码-block-LDPC decode VHDL source
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
ALTERA_MF_COMPONENTS
- VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础-VHDL
vhdl
- 用vhdl实现的抢答器程序。正弦波，锯齿波，三角波发生器程序。基于pwm技术的数码流水灯程序。计数器程序。-Responder with vhdl implementation process. Sine wave, sawtooth wave, triangle wave generator program. Pwm technology based on digital light process flow. Counter program.
verilog_frenqucy_div
- 使用verilog语言实现任意分频的设计，各位verilog学习者或者IC设计验证人员可以参考。-Verilog language use the design of any frequency, you verilog learners or who can refer to IC design verification.
QuartusII
- 在quartus2中实现过的VHDL源码。已经试用过。-Medium quartus2 at implementation of the VHDL source code too. Have tried them already.
VHDL
- 用VHDL编写的数字时钟，数码管显示时钟，已经通过编译-VHDL
12frequency
- 分频系数为12，输出信号的占空比为50 -Frequency factor of 12, the output signal duty cycle is 50