资源列表
operators
- cac toan tu thong dung duoc thiet ke trong vhdl
chap3
- 小例子,关于Verilog HDL语言的一些小练习,可供初学者进行参考.
vhdl
- 这是一个基于VHDL语言编程的电子琴源代码程序，希望可以帮到大家-This is a keyboard based on the VHDL programming language source code program, the desire to help everyone
TEST
- 这是一段VHDL代码，用于对FPGA开发环境的熟悉。-This is a VHDL .
sdh
- 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
tb_SCK_CLK_interface(VHDL
- 对时钟的编写，同事包括测试平台，可以实现正常的功能-The preparation of the clock, colleagues, including test platform, can achieve normal function
fifo
- 详细介绍了fifo深度计算的方法，fifo深度的计算是面试中常被问到的问题！-Fifo depth details of the method of calculation, fifo depth calculation is frequently asked interview questions!
divider
- 除法器，经过验证,性能优良，值得下载，应该是定点除法的-divider,it is verified and good performance
fifo24_cs8416
- my fifo prọ act in audio digital
DigitalClockSystem
- Pulser generate pulse
Eda1
- 程序在报告中，要 用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-e
Ch9
- 《Verilog HDL数字系统设计及仿真》第九章常见功能电路的HDL模型源代码-" Verilog HDL design and simulation of digital systems," Chapter IX common functional circuits HDL model source code