资源列表
Digital_stopwatch
- 秒表程序，FPGA实现，是在DE-2开发板上实现的-Digital stopwatch，FPGA，DE-2
cordic_vhdl1
- 利用cordic实现直角坐标与极坐标的转换，用vhdl实现-use cordic achieve very Cartesian coordinates with the conversion, with vhdl achieve
risc_cpu
- RISC_cpu，包括所有的模块与测试文件。是夏宇闻第二版书中的错误均已改正，运行正确后上传，请放心使用。-RISC_cpu, including all modules and test files. Xia Wen error of the second edition of the book have been correct, to run correctly upload, please feel free to use.
chap3
- 本程序是关于学习VERILOG语言的案例，方便读者快速掌握VERILOG语言的基本语法，操作等-This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
Generatedsinewave
- 把程序下载到FPGA中，使其能够产生正弦波，实现其工哪呢个-The process of downloading to the FPGA to enable it to have a sine wave, which can achieve its work months
register-vcode
- shift register verilog code
VHDLplj
- (1)设计4位十进制频率计测量范围: 1Hz～9999Hz (2）测量的数值通过4个数码管显示 (3）频率超过9999Hz时，溢出指示灯亮，可以作为扩大测量范围的接口-(1) the design of four decimal frequency measuring range: 1Hz ~ 9999Hz (2) measurement values through four digital tube display (3) the frequency of more than 999
division-verilog
- 文章详解介绍了用Verilog HDL语言编写任意倍偶数分频和奇数分频的原理以及源程序，都通过仿真，结果完全正确。-The article introduced with sep Verilog HDL language writing any times frequency and the odd points even points of the principle and the frequency source program, through the simulation, the r
SRAM
- 用memory compiler 生成的 512*8的SRAM，经过测试，可用进行读写-With SRAM memory compiler to generate 512* 8, tested, can read and write
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
VerilogBasicICDesign
- Verilog基本电路设计,包括时钟域同步、无缝切换、 异步FIFO、去抖滤波-Verilog basic circuit design, including clock domain synchronization, seamless switching, asynchronous FIFO, debounce filter
counter_20
- 20计数器，quartusII编写，VHDL语言-20 counters, quartusII writing, VHDL language