资源列表
memoryVHDLdesign
- memory VHDL design-memory VHDL design
VHDL_EXAMPLES
- VHDL例子集锦,很适合初学者-VHDL EXAMPLES
fracn09
- Clock generation perl to vhdl oijoij
2fsk
- 基于CPLD的数字通信系统2fsk 用VHDL形成2FSK信号-CPLD-based digital communications system 2fsk signal 2FSK formed with VHDL
2fsk-2psk
- 基于CPLD的数字通信系统 2fsk-2psk 用VHDL产生 2fsk-2psk信号-CPLD-based digital communications system 2fsk-2psk generated by VHDL signals 2fsk-2psk
2mxulie
- 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m
ask
- 基于CPLD的数字通信系统 ask序列 用VHDL产生 ask序列信号-CPLD-based digital communications system, ask the sequence generated by VHDL signal sequence ask
mqst
- 基于CPLD的数字通信系统曼切斯特用VHDL产生 曼切斯特信号-CPLD-based digital communications system Manchester Manchester signal generated by VHDL
VHDL
- VHDL代码集锦 VHDL常用的22个子程序源码-VHDL Collection VHDL code of the 22 sub-procedures commonly used source
65536
- (1) 计数器的输入为RST(复位),EN(使能),CLK(时钟),U_D(up_down加/减选择);输出为COUT(进位/借位输出),CQ(3:1)(数值输出); 范围65536。 -failed to translate
vga_control
- verilog语言 vga 控制 和显示功能-vga display
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
