资源列表
at7_ex03
- 使用FPGA内部的PLL产生时钟，计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
at7_ex04
- 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
at7_ex05
- 实现PC端通过UART发送数据到FPGA，FPGA将所接收到的数据同样是通过UART原本不动的发回给PC端。(The PC terminal sends data to FPGA through UART. FPGA sends the received data back to the PC end by UART.)
DLL_clock_generator
- DLL is useful for the ug and pg sdents tu
Aircon
- VHDL code for air con
pwm
- 本程序可以实现输出不同占空比（0-100）和不同频率的pwm波形；满足驱动不同硬件的需求；(This program can output PWM waveforms with different duty cycles (0-100) and different frequencies, and meet the needs of different hardware drivers.)
C5G_SRAM_RTL_Test
- 官网c5板子的SRAM工程，可以直接一直使用。(The SRAM project of official website C5 board can be used directly)
nhan 4 bit
- example about multiple booth 2 in vhdl
uart程序
- UART接口程序，UART字符发送函数，UART字符接收函数，主函数等(the connect of uart)
led
- verilog 控制 led灯 基于FPGA开发板(Verilog control LED lamp based on FPGA development board)
16QAM
- 可以实现随机序列和16QAM的仿真，verilog语言编程，modelsim和QUARTUS联合仿真(It can realize the simulation of random sequence and 16QAM, Verilog language programming, Modelsim and QUARTUS co simulation.)
jishuqi
- FPGA应用底层开发的逻辑单元slice连线实现计数器的功能，包含代码及仿真(FPGA applies the logic unit slice connection that is developed at the bottom to realize the function of counter, including code and simulation.)