资源列表
C5G_LPDDR2_RTL_Test
- LPDDR2工程，alteral的c5芯片，板子上验证过，可以直接用。(LPDDR2 project, alteral's C5 chip, has been verified on board and can be directly used.)
y1
- FPGA input clock frequency 50Mhz, try to design a frequency divider to realize 1Hz count signal. Requirements: writing design modules; Write the test model.
FIR
- 采用加法树设计8位乘法器，具有流水线结构7阶FIR滤波器，输入序列信号字长4位表示，并且是无符号数。(An adder tree is used to design the 8 bit multiplier, which has a pipelined 7 order FIR filter. The input sequence signal is 4 bits, and it is an unsigned number.)
辅导资料-HUST_HDL_Verilog课件
- 关于FPGA技术的相关说明，硬件描述语言与数字系统设计(Relevant instructions on FPGA Technology)
DB4CE15黑金原创教程
- 介绍黑金FPGA 的使用方法，从简到繁，慢慢学起(Introduction to the use of black gold FPGA method, simple to the complex, start slowly)
iir_2n_ip_float_demo
- 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
2016-17 IETE
- check the file, its the IETE pics
LCD_ML605
- Motor speed controller using VHDL
PhotoshopPortable
- command prompt too all
New folder
- verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.
state_machine
- a state machine in vhdl
ALU
- this is a simple arithmetic logic unit in vhdl