资源列表
can_v3_2
- XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)
扰码器Verilog
- 实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)
my_led_ip
- 四通道axi LED灯控制器，用于嵌入式系统中的一些功能指示(The four channel Axi LED lamp controller is used for some function instructions in the embedded system)
bpi
- bpi相关设置 vhdl中的bpi设置及相关介绍(in bpi using in fpga introduciton of bpi and using of fpga)
LMS_filter_Altera
- 2017电子竞赛e题软件部分,fpga实现(lms adaptive filter undergraduate electronic design contest)
intel fpga user manual
- quartus 官方使用手册，intelFPGA,原ALTERAFPGA(The official manual,the Intel fpga user manual)
test
- 利用xilinx公司开发的vivado平台中的IP核-rom，实现存储(Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.)
oo
- 利用xilinx公司开发的vivado平台，实现下变频功能(We use the vivado platform developed by Xilinx to realize the down conversion function.)
demo
- 利用xilinx公司开发的vivado平台，实现调用romIP核的功能(Using the vivado platform developed by Xilinx, the function of calling romIP core is implemented.)
one_1bit
- 利用xilinx公司开发的vivado平台，实现调用1bitpwm信号实现下变频的功能(Using the vivado platform developed by Xilinx, we can realize the function of calling down the 1bitpwm signal to realize the down conversion.)
HW1_alu_v1
- Arithmetic logic unit (ALU)是在電腦處理器之中其中一個組成單元,ALU 有 數學、邏輯、還有一些設計過的運算在電腦之中。(8-bit ALU Design is an unit of computer, it can process computation and logic.)
multi_key_dict-master
- You should upload 5 codes/documents files2