资源列表
INTERLEAVER
- 1/3,k=9的卷积码VHDL实现,在xilinx ise上仿真成功。-1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
Key_detect_code_based_Verilog
- 用Verilog hdl 语言编写的键盘检测驱动程序-Use Verilog HDL language programme keyboard test driver.
2_led
- 基于nios ide编程并下载至FPGA中的led灯闪亮程序-Based nios ide programmed and downloaded to the FPGA program led lights flashing
traffic
- traffic light control by FPGA Quartos
Memory-to-store-data
- Memory to store variable amount of data
manchester_encoding
- 用电压的变化表示0和1.规定在每个码元中间发生跳变.高→ 低的跳变表示0,低→ 高的跳变表示为1,也就是用01表示0,用10表示1.每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致.-With the voltage changes that have 0 and 1. Provides that each code element transitions occurring in the middle. High to low transi
cfft4
- fft radix-4 VHDL for expanding to any fourier transform
IS61LV10248
- IS61LV10248器件的modelsim 仿真模型-IS61LV10248 Verilog model for modelsim
function-of-adder32
- 这是一个32 bits carry-select-addeer.It s very new.-this is an adder with the function of 32bits adder.
SPI
- SPI接口程序 可以直接应用。 -SPI interface program can be applied directly.
bypasscolumn
- VHDL CODE FOR 4 BIT BYPASS COLUMN MULTIPLIER
uart
- This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.